Modern integrated circuits are fabricated using a wide variety of processes, many of which involve photolithographic methods. As the term is used herein, “integrated circuit” includes devices such as those formed on monolithic semiconducting substrates, such as those formed of group IV materials like silicon or germanium, or group III-V compounds like gallium arsenide, or mixtures of such materials. The term includes all types of devices formed, such as memory and logic, and all designs of such devices, such as MOS and bipolar. The term also comprehends applications such as flat panel displays, solar cells, and charge coupled devices.
As the feature size of integrated circuits has become smaller, new photolithographic methods have been instituted to enable these smaller feature sizes. One method is called dual pattern lithography. Dual pattern lithography uses multiple reticles (two or more) to expose a denser feature pattern (features closer together) than that which is possible using just a single reticle. This is accomplished by exposing a first set of features having a first spacing with a first reticle, and then interleaving a second set of features having a second spacing by exposure with a second reticle. By interleaving the feature sets in this manner, the spacing between the features of the two sets can be made closer than that which could otherwise be accomplished with features that are defined on a single reticle.
This process could be accomplished with more than two reticle sets as well, even though the name “dual pattern” tends to indicate a limitation of two reticles. Further, it is understood that the term “reticle” as used herein also includes “masks,” and vice-versa. Further, separately exposed patterns that originate from a single reticle are also contemplated by dual pattern lithography.
The use of dual pattern lithography brings new problems that are not present with conventional lithography. For example, the use of dual pattern lithography tends to severely affect both critical dimension and overlay tolerances because of lens/scanner induced errors and reticle pattern placement errors. These errors have been compensated for in the past by directly measuring the exposed pattern after it is printed on the substrate, and then using the measured error information to make changes in the setup of the exposure tool.
Unfortunately, this method requires substrates to be printed before the errors can be measured. Because such a procedure is time consuming, this trial and error process carries with it a greater than desirable cost.
What is needed, therefore, is a system that overcomes problems such as those described above, at least in part.